Function core::arch::mips64::__msa_fexupr_d
source · pub unsafe fn __msa_fexupr_d(a: v4f32) -> v2f64
🔬This is a nightly-only experimental API. (
stdarch_mips
#111198)Available on (MIPS or MIPS-64) and target feature
msa
and MIPS-64 only.Expand description
Vector Floating-Point Up-Convert Interchange Format Left
The right half floating-point elements in vector a
(four 32-bit floating point numbers)
are up-converted to a larger interchange format,
i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit.
The result is written to vector (two 64-bit floating point numbers).